Memory device having buried source/drain region and fabrication thereof

ABSTRACT

A method of fabricating a memory device having a buried source/drain region is provided, in which a dielectric layer and a word-line is sequentially formed on the substrate, then a buried source/drain region is formed in the substrate. After that, a barrier layer is formed on the exposed surface of the word-line, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion covering the buried source/drain region beside the word-line and crossing over the word-line.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwanapplication serial no. 90129018, filed Nov. 23, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of Invention

[0003] The present invention relates to a semiconductor device and thefabrication thereof. More particularly, the present invention relates toa memory device having a buried source/drain region and the fabricationthereof.

[0004] 2. Description of Related Art

[0005] The buried diffusion, e.g., the source/drain region or the buriedline, is regularly formed by implanting a high dosage of arsenic ions orphosphorous ions into the substrate and has a sheet resistance usuallylarger than 50 ohm/cm². Such a high sheet resistance will slow down thedevice. For example, the operation speed of a Mask ROM (mask read-onlymemory) or a NROM (nitride ROM) will be lowered if the buried bit-linehaving high resistance is used only.

SUMMARY OF THE INVENTION

[0006] Accordingly, a memory device having a buried source/drain regionand the fabrication thereof are provided in this invention to lower thesheet resistance of the source/drain.

[0007] Another object of this invention is to provide a memory devicehaving a buried source/drain region and the fabrication thereof. Thismethod can serve to increase the maximum linewidth of the word-linesince the sheet resistance of the source/drain can be lowered even ifthe buried source/drain region is smaller.

[0008] Another object of this invention is to provide a memory devicehaving a buried source/drain region and the fabrication thereof toenhance the operation speed of the memory device.

[0009] According to the above-mentioned objects and others, the methodof fabricating a memory device having a buried source/drain region inthis invention is described as follows. A dielectric layer is formed ona substrate, then a word-line is formed over the substrate, following bya buried source/drain region formed in the substrate. After that, abarrier layer is formed on the exposed surface of the word-line, then ametal layer is formed over the substrate. The metal layer is patternedto leave a portion of the metal layer covering the buried source/drainregion beside the word-line and crossing over the word-line. Since themetal layer is formed in parallel connection with the buried diffusion,the sheet resistance of the bit-line structure (metal layer+burieddiffusion) is lower than before and the operation speed of the memorydevice is therefore increased.

[0010] This invention also provides a method of fabricating a Mask ROMdevice. In this method) a dielectric layer is formed on a substrate,then a plurality of buried bit-lines are formed in the substrate and aplurality of word-lines that crossing over the buried bit-lines areformed over the substrate. Afterward, a barrier layer is formed on theexposed surfaces of the word-lines, then a metal layer is formed overthe substrate. The metal layer is patterned to leave a portion of themetal layer covering the buried bit-lines beside the word-lines andcrossing over the word-lines. Next, a coding process is performed toform a plurality of coding regions in the substrate.

[0011] In addition, this invention provides a method of fabricating aNROM (nitride ROM) device. In this method, a plurality of buriedbit-lines are formed in the substrate, then a trapping layer, such as anONO (silicon oxide/silicon nitride/silicon oxide) structure, is formedon a substrate. After that, a plurality of word-lines crossing over theburied bit-lines are formed over the substrate, then a barrier layer isformed on the exposed surfaces of the word-lines and a metal layer isformed over the substrate. The metal layer is patterned to leave aportion of the metal layer covering the buried bit-lines beside theword-lines and crossing over the word-lines.

[0012] In the preferred embodiments of this invention, the method offabricating a Mask ROM device having buried bit-lines is described. Inthis method, a gate insulator is formed on the substrate, then aplurality of gate structures, which are equal to the word-lines, areformed over the substrate. Subsequently, a barrier layer is formed onthe exposed surfaces of the gate structures, then an inter-layerdielectric layer is formed over the substrate. A lithography andimplantation process is performed to form a plurality of buriedbit-lines in the substrate, then the exposed inter-layer dielectriclayer is removed, following by a metal layer formed on the substrate.The metal layer is patterned to leave a portion of the metal layercovering the buried bit-lines beside the word-lines and crossing overthe word-lines.

[0013] Since a metal layer is formed in parallel connection with theburied diffusion, the sheet resistance of the new conductive structure(metal layer+buried diffusion) is lower than before. Besides, since thesheet resistance of the bit-line can be lowered by the metal layer evenif the buried bit-line is narrower, the maximum linewidth of theword-line can be increased and the operation speed can be enhanced.

[0014] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0016]FIG. 1 schematically illustrates the layout of the Mask ROM devicehaving buried bit-lines in the preferred embodiments of this invention;and

[0017]FIG. 2A˜10A and FIG. 2B˜10B schematically illustrate the flowchart of fabricating the Mask ROM device in the preferred embodiments ofthis invention, wherein

[0018]FIG. 2A and FIG. 2B schematically illustrate in their left partsthe cross-sectional views of the memory device area 20 along the sameline I-I in FIG. 1 after the initial steps, while the cross-sectionalviews of the periphery device area 22 are shown in the right parts ofFIG. 2A and FIG. 2B;

[0019]FIG. 3A and FIG. 3B are the cross-sectional views of the memorydevice area along the same line I-I and line II-II in FIG. 1,respectively, after the barrier layer is deposited;

[0020]FIG. 4A and FIG. 4B are the cross-sectional views of the memorydevice area along the same line I-I and line II-II in FIG. 1,respectively, after the first inter-layer dielectrics is deposited andpartially etched and after the second inter-layer dielectrics isdeposited;

[0021]FIG. 5A and FIG. 5B are the cross-sectional views of the memorydevice area along the same line I-I and line II-II in FIG. 1,respectively, after the lithography and implantation process of thebit-lines;

[0022]FIG. 6A and FIG. 6B are the cross-sectional views of the memorydevice area along the same line I-I and line II-II in FIG. 1,respectively, after the first and the second inter-layer dielectrics ispartially etched to expose the barrier layer;

[0023]FIG. 7A and FIG. 7B are the cross-sectional views of the memorydevice area along the same line I-I and line II-II in FIG. 1,respectively, after the barrier layer is partially etched;

[0024]FIG. 8A and FIG. 8B are the cross-sectional views of the memorydevice area along the same line I-I and line II-II in FIG. 1,respectively, after the metal layer is deposited and partially etched,

[0025]FIG. 9A and FIG. 9B are the cross-sectional views of the memorydevice area along the same line I-I and line II-II in FIG. 1,respectively, after the coding process of the Mask ROM; and

[0026]FIG. 10A and FIG. 10B are the cross-sectional views of the memorydevice area along the same line I-I and line II-II in FIG. 1,respectively, after the third interlayer dielectrics is deposited.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Referring to FIG. 1, which schematically illustrates the layoutof the Mask ROM device having buried bit-lines in the preferredembodiments of this invention.

[0028] As shown in FIG. 1, the Mask ROM device of this preferredembodiment includes the word-lines 100 on the substrate 10, the buriedbit-lines 102 in the substrate 10 and being vertical to the word-lines100, and the metal layers 104 over the buried bit-lines 102 and crossingover the word-lines 100. The metal layer 104 is in parallel connectionwith the buried bit-line 102 and is preferably made from tungsten. Then,the process steps of fabricating such a memory device are described indetail in the following paragraphs with the accompanying drawings.

[0029] Referring to FIG. 2A and FIG. 2B, which schematically illustratein their left parts the cross-sectional views of the memory device area20 along the same line I-I in FIG. 1 after the initial steps, while thecross-sectional views of the periphery device area 22 are shown in theright parts of FIG. 2A and FIG. 2B.

[0030] As shown in FIG. 2A and FIG. 2B, a dielectric layer 202 is formedon the substrate 200 to serve as a gate insulator, then the gatestructures 204 that act as the word-lines are formed over the substrate200 and in the memory device area 20. The method of making the gatestructures 204 is, for example, to form a conductive layer 206 and acapping layer 210 sequentially over the substrate 200, then pattern thecapping layer 210 and the conductive layer 206. The materials of theconductive layer 206 and the capping layer 210 are, for example,polysilicon and silicon nitride, respectively. In addition, it is morepreferred to interpose a polycide layer 208 between the conductive layer206 of polysilicon and the capping layer 210.

[0031] Referring to FIG. 2B again, spacers 212 are then formed on theside-walls of the gate structures 204 in the memory device area 20 andin the periphery device area 22, then a source/drain region 214 isformed in the substrate 200 in the periphery device area 22.

[0032] Referring to FIG. 3A and FIG. 3B, which are the cross-sectionalviews of the memory device area along the same line I-I and line II-IIin FIG. 1, respectively, after the barrier layer is deposited

[0033] As shown in FIG. 3A and FIG. 3B, a barrier layer 216 is formedover the substrate 200 to cover the gate structures 204, wherein thebarrier layer 216 can be a plurality of barrier spacers 216 b (see FIG.7B) formed by depositing and etching back a barrier material layer. Thebarrier material layer covers the surface of the substrate 200 and theexposed surfaces of the gate structures 204 and comprises, for example,silicon nitride.

[0034] Referring to FIG. 4A and FIG. 4B, which are the cross-sectionalviews of the memory device area along the same line I-I and line II-IIin FIG. 1, respectively, after the first inter-layer dielectrics isdeposited and partially etched and after the second inter-layerdielectrics is deposited.

[0035] As shown in FIG. 4A and FIG. 4B, a first inter-layer dielectrics(ILD1) 218, such as a silicon oxide layer, is formed on the substrate200. Afterward, the first interlayer dielectrics 218 is etched until thebarrier layer 216 is exposed, which is achieved by, for example,polishing the first inter-layer dielectrics 218 by chemical mechanicalpolishing (CMP) with the barrier layer 216 as a stop layer. A secondinter-layer dielectrics (ILD2) 220, such as a silicon oxide layer, isformed over the substrate 200 to cover the first inter-layer dielectrics218 and the barrier layer 216.

[0036] Referring to FIG. 5A and FIG. 5B, which are the cross-sectionalviews of the memory device area along the same line I-I and line II-IIin FIG. 1, respectively, after the lithography and implantation processof the bit-lines.

[0037] As shown in FIG. 5A and FIG. 5B, an anti-reflection coating (ARC)222 is formed on the second inter-layer dielectrics 220, then apatterned photoresist layer 224 is formed on the anti-reflection coating(ARC) 222, wherein the photoresist layer 224 exposes a portion of theanti-reflection coating 222. Subsequently, the buried bit-lines 226 areformed in the substrate 200 by performing an implantation with thephotoresist layer 224 as a mask.

[0038] Referring to FIG. 6A and FIG. 6B, which are the cross-sectionalviews of the memory device area along the same line I-I and line II-IIin FIG. 1, respectively, after the first and the second inter-layerdielectrics are etched to expose a portion of the barrier layer.

[0039] As shown in FIG. 6A and FIG. 6B, the exposed first inter-layerdielectrics 218 and the exposed second inter-layer dielectrics 220 areetched away with the photoresist layer 224 as a mask to expose a portionof the barrier layer 216. After that, the photoresist layer 224 isremoved to expose the previously covered portions of the secondinter-layer dielectrics 220 a and the anti-reflection coating 222 a.

[0040] Referring to FIG. 7A and FIG. 7B, which are the cross-sectionalviews of the memory device area along he same line I-I and line II-II inFIG. 1, respectively, after the barrier layer is partially etched.

[0041] As shown in FIG. 7A and FIG. 7B, a portion of the exposed barrierlayer 216 is etched away, then the etching process is continued toremove the exposed gate insulator 202 and to expose a portion of theburied bit-lines 226.

[0042] Referring to FIG. 8A and FIG. 8B, which are the cross-sectionalviews of the memory device area along the same line I-I and line II-IIin FIG. 1, respectively, after the metal layer is deposited andpartially etched.

[0043] As shown in FIG. 8A and FIG. 8B, the remaining anti-reflectioncoating 222 a is removed, then a metal layer 228, which preferablycomprises tungsten, is formed over the substrate 200. After that, themetal layer 228 is etched until the second inter-layer dielectrics 220 ais exposed, which can be done by, for example, polishing the metal layer228 by chemical mechanical polishing (CMP) with the second inter-layerdielectrics 220 a as a stop layer.

[0044] Referring to FIG. 9A and FIG. 9B, which are the cross-sectionalviews of the memory device area along the same line I-I and line II-IIin FIG. 1, respectively, after the coding process of the Mask ROM.

[0045] As shown in FIG. 9A and FIG. 9B, a coding process is thenperformed to form a ROM code 230 in the substrate 200. Alternatively,the coding process can be performed before the buried bit-lines 226 areformed in the substrate 200.

[0046] Referring to FIG. 10A and FIG. 10B, which are the cross-sectionalviews of the memory device area along the same line I-I and line II-IIin FIG. 1, respectively, after the third inter-layer dielectrics isdeposited.

[0047] As shown in FIG. 10 and FIG. 10B, a third inter-layer dielectrics232 is then formed over the substrate 200. The following back-endprocess is omitted here since it should be well known to those skilledin the art.

[0048] Since a metal layer is formed in parallel connection with theburied diffusion, such as a buried bit-line 226, in this invention, thesheet resistance of the whole bit-line (buried bit line +metal layer) islower than before. Besides, since the sheet resistance of the wholebit-line can be lowered even if the buried bit-line is narrower, themaximum linewidth of the word-line can be increased and the operationspeed of the memory device can be enhanced.

[0049] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention,In view of the foregoing, it is intended that the present inventioncovers modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A method of fabricating a memory device having aburied source/drain region, comprising the steps of providing asubstrate; forming a dielectric layer on the substrate, forming aword-line over the substrate; forming a buried source/drain region inthe substrate; forming a barrier layer on a exposed surface of theword-line; forming a metal layer over the substrate; and patterning themetal layer to leave a portion of the metal layer covering the buriedsource/drain region beside the word-line and crossing over theword-line.
 2. The method of claim 1, wherein the metal layer comprisestungsten.
 3. The method of claim 1, wherein the method of forming theword-line comprises the steps of: forming a conductive layer over thesubstrate; forming a capping layer over the conductive layer; patterningthe capping layer and the conductive layer to form the word-line; andforming a spacer on a side-wall of the word-line.
 4. The method of claim3, wherein the conductive layer comprises polysilicon.
 5. The method ofclaim 4, further comprising a step of forming a polycide layer on theconductive layer after the step of forming the conductive layer over thesubstrate.
 6. The method of claim 3, wherein the capping layer comprisessilicon nitride.
 7. The method of claim 1, wherein the method of formingthe barrier layer comprises the steps of: forming a barrier materiallayer on the substrate to cover a surface of the substrate and a exposedsurface of the word-line; and etching back the barrier material layer toform a barrier spacer on a side-wall of the word-line.
 8. The method ofclaim 7 wherein the barrier material layer comprises silicon nitride. 9.A method of fabricating a mask read-only memory (Mask ROM), comprisingthe steps of: providing a substrate; forming a dielectric layer on thesubstrate; forming a plurality of buried bit-lines in the substrate;forming a plurality of word-lines over the substrate and crossing overthe buried bit-lines; forming a barrier layer on exposed surfaces of theword-lines; forming a metal layer over the substrate; patterning themetal layer to leave a portion of the metal layer covering the buriedbit-lines beside the word-lines and crossing over the word-lines; andperforming a coding process to form a plurality of coding regions in thesubstrate.
 10. The method of claim 9, wherein the coding process isperformed before the step of forming the buried bit-lines in thesubstrate.
 11. The method of claim 9, wherein the coding process isperformed after the step of patterning the metal layer.
 12. The methodof claim 9, wherein the metal layer comprises tungsten.
 13. The methodof claim 9, wherein the method of forming the word-lines comprises thesteps of: forming a conductive layer over the substrate; forming acapping layer over the conductive layer; patterning the capping layerand the conductive layer to form the word-lines; and forming a pluralityof spacers on side-walls of the word-lines.
 14. The method of claim 13,wherein the conductive layer comprises polysilicon.
 15. The method ofclaim 14, further comprising a step of forming a polycide layer on theconductive layer after the step of forming the conductive layer over thesubstrate.
 16. The method of claim 13, wherein the capping layercomprises silicon nitride.
 17. The method of claim 9, wherein the methodof forming the barrier layer comprises the steps of: forming a barriermaterial layer on the substrate to cover a surface of the substrate andexposed surfaces of the word-lines; and etching back the barriermaterial layer to form a plurality of barrier spacers on side-walls ofthe word-lines.
 18. The method of claim 17, wherein the barrier materiallayer comprises silicon nitride.
 19. A method of fabricating a nitrideread-only memory (NROM), comprising the steps of: providing a substrate;forming a plurality of buried bit-lines in the substrate; forming atrapping layer on the substrate; forming a plurality of word-lines onthe trapping layer and crossing over the buried bit-lines; forming abarrier layer on exposed surfaces of the word-lines; forming a metallayer over the substrate; and patterning the metal layer to leave aportion of the metal layer covering the buried bit-lines beside theword-lines and crossing over the word-lines.
 20. The method of claim 19,wherein the trapping layer comprises an ONO (silicon oxide/siliconnitride/silicon oxide) structure.
 21. The method of claim 19, whereinthe metal layer comprises tungsten.
 22. The method of claim 19, whereinthe method of forming the word-lines comprises the steps of: forming aconductive layer over the substrate; forming a capping layer over theconductive layer; patterning the capping layer and the conductive layerto form the word-lines; and forming a plurality of spacers on side-wallsof the word-lines.
 23. The method of claim 22, wherein the conductivelayer comprises polysilicon.
 24. The method of claim 23, furthercomprising a step of forming a polycide layer on the conductive layerafter the step of forming the conductive layer over the substrate. 25.The method of claim 22, wherein the capping layer comprises siliconnitride.
 26. The method of claim 19, wherein the method of forming thebarrier layer comprises the steps of forming a barrier material layer onthe substrate to cover a surface of the substrate and exposed surfacesof the word-lines; and etching back the barrier material layer to form aplurality of barrier spacers on side-walls of the word-lines.
 27. Themethod of claim 26, wherein the barrier material layer comprises siliconnitride.
 28. A memory device having a buried source/drain, comprising. aword-line on a substrate; a buried source/drain in the substrateperpendicular to the word-line; a dielectric layer between the word-lineand the substrate; a metal layer crossing over the word-line and beingin parallel connection with the buried source/drain; and a barrierspacer between the word-line and the metal layer.
 29. The memory deviceof claim 28, wherein the metal layer comprises tungsten.
 30. The memorydevice of claim 28, wherein the word-line comprises polysilicon.
 31. Thememory device of claim 28, wherein the barrier spacer comprises siliconnitride.
 32. The memory device of claim 28, wherein the word-linecomprises: a conductive layer, a cap layer on the conductive layer; anda spacer on side-walls of the cap layer and the conductive layer. 33.The memory device of claim 32, wherein the conductive layer comprisespolysilicon.
 34. The memory device of claim 33, further comprising apolycide layer between the conductive layer and the cap layer.
 35. Thememory device of claim 32, wherein the cap layer comprises siliconnitride.